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MC13760
GSM/DCS/TDMA/AMPS Multi-Protocol Transceiver
The MC13760 Multi-Protocol, Multi-Band Digital Transceiver IC combines, on a single Advanced BiCMOS chip, the major building blocks required for next generation multi-purpose, multi-band wireless products. The device includes the majority of the circuitry necessary for IF signal processing between the RF front end and the DSP and backend. The MC13760 contains two fractional-N synthesizers, a re-configurable zero IF receiver with programmable bandwidth, receive A/D conversion, multi-rate data interface to the baseband DSP, direct launch digital modulator, full transmit support circuits, and general purpose support circuits such as D/A and A/D converters, battery save and tri-state control switches. Intended for use in a combined GSM/TDMA/AMPS/iDEN portable wireless phone product in the 800/900/1800/1900 MHz bands. The MC13760 can be used over a wide range of RF and IF frequencies. The main PLL prescaler input is usable to over 2.0 GHz and the IF quadrature downconverter operates up to 400 MHz. The MC13760 has separate receive IF inputs and a common zero-IF IQ receiver for TDMA and for GSM accommodating the receiver architectural need to use different IF frequencies and filters without the need for additional switches. * Receiver Functions for all GSM/DCS/TDMA IS-136/AMPS Modes and Frequencies Including GPRS * Direct Interface to Motorola Baseband Processors, such as the DSP56690 through a Common Programming and Data Interface * Main Three Accumulator (24-Bit) Fractional-N Synthesizer * Resolution Capability of 6.0 Hz * Dual-Mode Charge Pump Output for TDMA TX VCO and all RX * Independent Charge Pump Output for the GSM/DCS TX VCO * GMSK Lookup ROM for Direct Transmission in GSM/DCS Mode * Digital 16-Bit Automatic Frequency Control
MULTI-PROTOCOL TRANSCEIVER
SEMICONDUCTOR TECHNICAL DATA
PLASTIC PACKAGE CASE 1285 (BGA-104)
ORDERING INFORMATION
Device MC13760 Operating Temperature Range TA = -40 to 85C Package BGA-104
* * * * * * * * *
Secondary Three Accumulator (24-Bit) Fractional-N Synthesizer for use as an Accurate Frequency-Corrected Clock in GSM, or as an Additional Low Frequency LO Coarse Tuning of the VCO(s) via a 6-Bit D/A with Adapt Operates at 2.75 V Deep Sleep Mode with Current as low as 50 A Versatile Frequency Generation including Linear and Constant Envelope Modulation Paths, Ramp and Power Level Control, Direct Gain Control of the RFPA in the TDMA Mode D/A Conversion of TDMA TXI and TXQ Reference Crystal Oscillator with a Buffered Output, Compensation/Fine Tuning via 9-Bit D/A Receiver Gain Adjustment and Bandwidth Down to 6.0 kHz Programmed over the SPI Bus A/D Conversion of RXI and RXQ to 8-Bit or 10-Bit Resolution Types of Applications * GSM/DCS/TDMA/AMPS Global Roaming Multiband Cellular Telephone * VHF/UHF 2-Way or Trunked Radio, iDEN, Tetra, or Satellite Communication Radios or Telephones * Hand-Held Wireless PDA's * Wireless LAN's, Industrial Devices, ISM Band Products * Any New Device Containing Some Combination of the Above Functions
(c) Motorola, Inc. 2000 Rev 0
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
1
MC13760
Figure 1. MC13760 Detailed Block Diagram
DMKGNDDIG DMKVCCDIG
DMKGND
DMKVCC
BBEGND
BBEVCC
DCLICIN
AGCGND
AGCVCC
DCLICP
AGC Control
SPI Control
VACBYP
AGC
VAC
On Channel AGC Det.
RFA0 PRAVCC1 PREINI PREINIB PRAGND PRAVCC2 PREINGB PREING PRAGNDDIG LOIN DCLQCP
Step Alternator Control
DCOCL AGC Warp On Channel AGC Det. I 1 Pole 2 Pole 2 Pole 2 Pole NVCC NGND
Step Atten
AGC Amp Q Step Atten 1 Pole 2 Pole 2 Pole 2 Pole
QVCC QGND
+2 Quadrature Generator DCOCL
DCLQCIN REFVCC TCAPP TCAPM CREF REFGND Internal Reference & Bias 8 24 Accumulator #1 PRSCIN Programmable Divider 26 MHz VCOCT2 VCOCT1 XTALWARP Third Order Passive Filter OSCVCC OSCGND XTALBASE 26 MHz XTALEMIT CPGITR ADAPT CPGT MNCPGND TBD Order Passive Filter MNCPGND MAINVCC MAINGND AOCDRIVE Dual Mode Charge Pump Wideb and Charge Pump Reference Oscillator 4 +10/ +26 +1/ +2 86 Recombination Logic Adapt SPI 6 Bit Control D/A SPI 9 Bit Control D/A Phase Detector Startup Accumulator #3 2 4 2 2 26 MHz 6 Recombination Logic Accumulator #2 24 Bit Adder Addressable Shift Register SPII SPICLK CEX
Tracking Loop & BB Filter BW Control
Adapt Timing
S/H S/H S/H AGCI SERIALVCC SERIALGND
Battery Save
DIG_AFC Enable Battery Save
3:1 Input Mux
10 Bit, or 8 Bit Cyclic A/D
Receive Data Register
SRD RXACQ STD TXCLK/SCK RSTB TXE/TXKEY RXCLK RXFS/SFS TSLOT
Fine Channel 24 AFC_SEL 32 16 LSB Look-Up ROM TX DATA Buffer Start DO Clk 4.333 MHz DQ dk
Transmit Data Register Comb Filter Comb Filter
13.0 or 16.8 MHz IREF Clock Generation & Control Logic
B6
B16
8 Bit D/A
8 Bit D/A
Sw. Cap Filter +13/ +17/ +26/ +34 +65/ +84/ +130/ +168 PtC 200 kHz 24 Accumulator #1 Accumulator #2 Cont. Time Filter
Sw. Cap Filter Clock Gen.
TSLOTB TCLK TCLKB 1.0, 2.4 or 2.6 MHz CLKGENIN OUTI OUTIB OUTQ OUTQB
Cont. Time Filter
PtA +7/ +14/ +21/ +28
PtB
Programmable Divider From PtD 3 From PtA From PtA Control Logic 2 16 6 From PtB +1/+2/ +3/+4 MUX
Accumulator #3 SPII SPICLK CEX 8 400 KHz Reference 3 +1/ +2/ +3/ +4 Phase Detector/ +N Charge Pump 13.0 - 16.8 MHz or 26.0 - 33.6 MHz 5 49 Test Multiplex (2 Outputs) From PtD 62 62 Output Enable D or A 22 8 Bit D/A
DMCS VBLIN ASW VCNTO PtD Addressable Shift Register
CLKGENIN
MUX
MUX
8X6 3 Bit 6 Bit 6 Bit Cosine D/A 6 Reg 6 Lookup 3 Counter 8 Bit D/A 8 Bit 8 Bit Reg 8 Counter 8 5 Bit 5 Reg Super Filter
From TXE/ PtC TXKEY
8
IREF
Mixer & Preamp Current IF Control Channel AFC Addressable Shift Register SPII SPICLK CEX
SPI REG
5 Bit D/A
5
62
REFPLLGND
TXKEYOUT
PLLCPVCC
PLLBASE
OSCENB
PLLEMIT
CLKSEL
CLKOUT
SEBYP
SEGND
DETSW
SFVCC
SFOUT
PLLCP
TEST1
TEST2
TESTD
SATDET
REFPLLVCC
GPO1
TM
Tark Circuit
Loop Filter
2
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
LONCGND
LONCVCC
GPO2
GPO3
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MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
BALL # C10 B10 A10 C11 B11 A11 D9 D8 D6 D4 D3 D2 D1 C9 C8 C7 C6 C5 C4 C3 C2 C1 B9 B8 B7 B6 B5 B4 B3 B2 B1 A9 A8 A7 A6 A5 A4 A3 A2 A1 TESTD/GPO4 OUTI PKGGND1 TEST1/EERI TEST2/EERQ DMXVCCDIG LOIN QGND TCLKB CLKSEL OUTQB TCAPM DCLQCIN DCLICIN BBFVCC PRAVCC1 DMXGNDDIG DMXVCC TCLK REFVCC REFGND TCAPP GPO3/test_so2 DCLICP PRAVCC2 PREINI PREING DMXGND RFA0 TSLOT TSLOTB OUTIB OUTQ CREF DCLQCP BBFGND PREINIB PREINGB PRAGND PRAGNDDIG BALL NAME Digital test point. (Various digital signals are MUX'd to this pin. Output is determined by programming of test bits.) Or SPI port expansion 4. TDMA I channel analog transmit data. Ground for the package flag (no direct connection to die). Supply for the quadrature generator. Input port for the second LO VCO signal. Quiet analog ground for the PA D/A and the data processing circuits. TDMA low level transmit clock. TDMA Q channel analog transmit data. Differential reference capacitor. DC Offset Correction Loop (output) capacitor - TDMA - Q channel DC Offset Correction Loop (output) capacitor - TDMA - I channel Supply for the baseband filters. Supply for the preamp. Ground for the mixer substrate and quadrature generator. Supply for the mixer. TDMA low level transmit clock. Supply for the internal reference. Ground for the internal reference. Differential reference capacitor. SPI port expansion 3. Or scan data output for MODROM module. DC Offset Correction Loop (input) capacitor - I channel Supply for the preamp output stage. TDMA IF preamp input. GSM IF preamp input. Ground for the mixer. TDMA low level transmit slot. TDMA low level transmit slot. TDMA I channel analog transmit data. TDMA Q channel analog transmit data. Bypass capacitor for the bandgap regulator. DC Offset Correction Loop (input) capacitor - Q channel Ground for the baseband filters. TDMA IF preamp input. GSM IF preamp input. Ground for the preamp. Ground for the preamp substrate. Test input/MUX 1 output. (Various signals are buffered and MUX'd to this pin. Output signal is determined by programming of test bits.) Or with EER active, TDMA I channel transmit data. Test input/MUX 2 output. (Various signals are buffered and MUX'd to this pin. Output signal is determined by programming of test bits.) Or with EER active, TDMA Q channel transmit data. Selects the source for the clock output to the digital circuitry of the radio as either the crystal reference/divided crystal reference or the Step Up PLL/divided Step Up PLL. A low on this pin selects the crystal reference/divided crystal reference. A high on this pin selects the Step Up PLL/divided Step Up PLL. Integrated weak pulldown. RF attenuator 0 control line. (This line is a driver for an external RF attenuator.)
Table 1. BGA Contact Identification
MC13760
DESCRIPTION
Digital Test Point Digital Output Analog Output Pkg Ground Supply 2.775 V RF Input Ground Analog Output Digital Input Analog Output Analog Analog Output Analog Output Supply 2.775 V Supply 2.775 V Ground Supply 2.775 V Analog Output Supply 2.775 V Ground Analog Digital Output Analog Input Supply 2.775 V RF Input RF Input Ground Digital Output Analog Output Analog Output Analog Output Analog Output Analog Analog Input Ground RF Input RF Input Ground Ground
Analog Test Point
Analog Test Point
SIGNAL TYPE
3
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Table 1. BGA Contact Identification (continued)
DESCRIPTION BALL # D10 D11 E1 E2 E3 E9 BALL NAME SIGNAL TYPE QVCC Quiet analog supply for the PA D/A and the data processing circuits. Supply 2.775 V Ground Analog NGND VAG Noisy analog ground for the VCO D/A, AOC D/A and the data processing circuits. Analog ground. AGCGND VAGBYP NVCC RSTB TM Ground for the AGC. Ground Analog Bypass capacitor for the analog ground voltage. Noisy analog supply for the VCO D/A, AOC D/A and the data processing circuits. Reset. Low true input. Integrated weak pullup. Enable for the internal scan test. Supply for the AGC. Supply 2.775 V Digital Input Digital Input E10 E11 F1 F2 F3 F4 F8 F9 AGCVCC Supply 2.775 V Digital Output Analog TXKEYOUT/test_so4 AGC Conditioned TXKEY out. Or scan data output for reference clock module. Capacitor for the TDMA AGC. PKGGND2 PKGGND3 Ground for the package flag (no direct connection to die). Ground for the package flag (no direct connection to die). Pkg Ground Pkg Ground PLLCPVCC CLKOUT Supply for the Step Up PLL phase detector and charge pump. Supply 5.0 V F10 Clock output to the digital circuitry of the radio. Ranges are 13.0 to 16.8 MHz, or 26.0 to 33.6 MHz. The actual frequency provided will depend upon the configuration of the Step Up PLL and the SPI selected configuration of the MC13760. Charge pump output for the Step Up PLL. Main LO prescaler input. Analog Output F11 G1 G2 G3 G9 PLLCP Analog Output RF Input Ground PRSCIN MAINGND Ground for the main prescaler and divider. AOCDRIVE PLLEMIT Output to the PA bias circuitry drive input. (Output drive impedance is 620 Ohms.) Emitter of the oscillator transistor for the Step Up PLL. Supply for the Step Up PLL VCO and dividers. Analog Output RF Output G10 G11 H1 H2 H3 H4 H6 H8 H9 REFPLLVCC Supply 2.775 V RF Input PLLBASE/vco_clk SATDET/test_si4 GPO2/test_so8 MAINVCC Base of the oscillator transistor for the Step Up PLL. Or scan clock input for VCO clock zone. Input indicating saturation. Or scan data input for reference clock module. Digital Input SPI port expansion 2. Or Main PLL Adapt Timer output. Or scan data output for SSI module. Supply for the main prescaler and divider. Digital Output Supply 2.775 V Supply 5.0 V Pkg Ground Digital Input Digital Input Ground MNCPVCC PKGGND4 Supply for the main phase detector and charge pump. Ground for the package flag (no direct connection to die). TXE/TXKEY/test_si8 RXACQ/test_si7 REFPLLGND SERIALVCC Transmit slot enable in TDMA mode; digital input to start/stop the PA Control sequence in GSM mode. Or scan data input for SSI module. Serial bus enable. Or scan data input for 5 bit and 8 bit xtal clock dividers. Ground for the Step Up PLL. H10 H11 J1 J2 J3 J4 J5 Supply for the SSI and SPI serial communication ports. Supply 1.8 -- 2.775V Digital Output GPO1/test_so1 VCOCT2 SPI port expansion 1. Or Coarse Tune Adapt Timer output. Or scan data output for main Frac-N. High current (ADAPT) output of the 6 bit main RX VCO Coarse Tune D/A. Output to the PA control circuitry power range input (open drain). Or scan data input for main Frac-N. Supply for the super filter. Analog Output Analog Output DETSW/test_si1 SFVCC Supply 2.775 V Digital Input ASW/sc_inp1 TDMA antenna switch control input. Or scan data input for reference clock Frac-N accumulator module.
MC13760
4
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
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Table 1. BGA Contact Identification (continued)
DESCRIPTION BALL # J6 J7 J8 J9 BALL NAME SIGNAL TYPE VCNTO TDMA RFPA gain control voltage output. Supply for the crystal oscillator. Analog Output OSCVCC Supply 2.775 V Analog Output Digital Input XTALWARP OSCENB Output of the 9 bit WARP D/A to be used for compensation/correction of the reference crystal frequency. Digital input used to control the crystal oscillator circuit. A logic low selects the internal oscillator. Integrated weak pulldown. SSI RX clock in GSM mode; not used in TDMA mode. Or scan data output for transmit power amp control module. J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 RXCLK/test_so3 SRD/test_so6 VCOCT1 Digital Output Digital Output SSI receive data. Or scan data output for Adapt Generator module. Low current output of the 6 bit main RX VCO Coarse Tune D/A. Ground for the main phase detector and charge pump. Ground for the super filter. Bypass capacitor for the super filter. (1.0 f) Ground for the crystal oscillator. Analog Output Ground Ground Analog MNCPGND SFGND SFBYP OSCGND Ground XTALBASE/sc_clk26 LOGICVCC CEX Crystal oscillator base. Or scan clock input for xtal clock zone. RF Input Supply for the main synthesizer logic, adapt control and test MUXs. Digital input that latches in the SPI data. (Low Active) SPI clock input. Supply 2.775 V Digital Input Digital Input Digital Input SPICLK K10 K11 STD/test_si3 SSI transmit data. Or scan data input for transmit. TXCLK/SCK/test_so5 Bit clock for TX data transfer in GSM mode. Bit clock for RX and TX data transfer in TDMA mode. Or scan data output for reference clock Frac-N accumulator module. Synthesizer output to adapt the loop filter for the main PLL. Charge pump output for the main TX LO (GSM). Digital Output L1 L2 L3 L4 L5 L6 L7 L8 L9 ADAPT CPGT Analog Output Analog Output Analog Output Analog Output Analog Output RF Output Ground Ground CPGITR SFOUT VBLIN Charge pump output for the main RX LO (GSM, TDMA TX and RX). Super filter output. (45 mA max) (bypass with 0.01 f) TDMA RFPA bias control voltage output. Crystal oscillator emitter. XTALEMIT LOGICGND Ground for the main synthesizer logic, adapt control and test MUXs. Ground for the SSI and SPI serial communication ports. SPI data input. SERIALGND SPII Digital Input Digital Input L10 L11 DMCS/test_si2 Digital input that starts the GSM TX modulation. Or scan data input for MODROM module. RXFS/SFS/test_so7 RX SSI frame sync in GSM mode; SSI frame sync in TDMA mode. Or scan data output for 5 bit and 8 bit xtal clock dividers. Digital Output
MC13760
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
5
MC13760
OUTLINE DIMENSIONS
PLASTIC PACKAGE CASE 1224B-01 (BGA-104) ISSUE B X Y D
LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. MILLIMETERS MIN MAX 0.95 1.30 0.20 0.34 0.94 REF 0.30 0.50 8.00 BSC 8.00 BSC 0.80 BSC
M K
E
M 0.20
DIM A A1 A2 b D E e
8X 9 8 7 4 3 2
e
1 A B C D E F G H J
METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA
5 A A2 0.30 Z
8X
e
A1
81X
Z
4
0.15 Z
3
81X
b 0.25 0.10
M M
ROTATED 90 _ CLOCKWISE
DETAIL K
ZXY Z VIEW M-M
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6
MC13760PP/D MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA

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